The invention relates to a calculating unit for serial multiplication of a binary multiplicand with a binary multiplier.
The problem of multiplying different multiplicands with fixed multipliers arises in the processing of digital values. One example is the digital filter in which value sequence taken from a continuous signal and obtained by quantizing are subjected to arithmetical operations, such as addition, subtraction and multiplication with constant factors. Exemplary embodiments of such filters are represented for example in "Nachrichtetechnische Zeitschrift" June 1972, p. 289-298.
For the execution of serial multiplication, multiplier units are known (IEEE Transactions Vol. AU 16, 1968, No. 3 p. 413-421) in which a flip-flop chain is arranged in the input line for the multiplicand. The adders directly follow one another. The lower inputs of the adders are blocked in a specific time sequence by additional pulses which must be specially produced. As a consequence the lower product digits are suppressed actually during the calculation of the intermediate results. The multiplicands can directly follow one another without disturbing the product formation. It is not possible to change factors after each multiplicand is input. In the case of large numbers of bits the lining up of the full adders directly next to one another produces long transit times which limit the maximum operating frequency of the calculating unit. The upper frequency limit can only be extended by the interposition of individual flip-flops for the purpose of transit time coupling and the product appears one word length later.
Although the described multiplier unit can be employed universally since each arbitrary actor &lt;.vertline.1.vertline. can be set with the accuracy of the given bit digits, the material outlay is very great.
Furthermore an earlier German Offenlegungsschrift No. 22 14 257 proposes a calculating unit for the execution of multiplications, in which an incoming shift register is provided to receive the multiplicand bits incoming in serial form. On the arrival of a control pulse said bits are transferred in parallel into an output shift register. At the storage cells at which the associated multiplier exhibits a binary one the output shift register is provided with tappings, wherein the course from the higher value to the lower value digits of the multiplicand is selected to be the reverse. Then at the k-th tapping, the product 2.sup.-.sup.k times the multiplicand is present in serial form and can possibly be further processed in adder chains.
However on account of the complexity of their circuits, the shift register (preferably JK flip-flops) which are employed are elements which exhibit a high electrical power loss. If possible they should be in as small a number as possible. Also, for the parallel transfer of the bits of the multiplicand from the input-into the output register a transfer pulse train is employed which falls precisely between two pulses of the shift pulse train. The time available for the lowest value bit of the multiplicand is shortened for the following further processing (addition of the sub-products) so that at higher processing speeds calculating errors may occur. As the same pulse is also used to input the rounding bit into the carry store of the adders, only a very short processing time is available for the rounding bit.
The following adder chains require, for the addition of the subproducts, fine transit times which limit the maximum bit sequence, in particular in the case of a number of added sub-products without pulse-train-synchronous decoupling by means of interposed storage flip-flops.